Description

Job responsibilities:

Implement scan insertion, ATPG pattern generation, Memory and logic bist implementation
Perform DFT simulations and analyze results to ensure test coverage and quality.
Debug and resolve DFT-related issues throughout the design process.

Job qualification:

Senior DFT engineer with 4+ years of experience in SoC DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG, LBIST.
The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools.
The engineer needs to have hands-on experience in scan insertion, JTAG, LBIST, ATPG DRC and coverage analysis, Simulation debug with timing/SDF.
Must have worked on one SoC at least, from start to end.
Must be proactive, collaborative and detail-oriented capable of exercising independent judgment
Strong expertise in Post Silicon Readiness (Pattern Generation) and Silicon Debug.
The engineer with experience on debug and root cause the problem in simulation failures.
BE/ME/B.Tech/M.Tech from reputed institutes
Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills
Show an engaged curiosity, a will to understand the mechanisms behind the effects, an eagerness to constantly learn and improve

#LI-2734

Senior DFT Engineer